| 摘要 |
A digital delta-sigma modulator for controlling a multi-modulus divider in a fractional-N frequency synthesizer features cascaded delta-sigma modulator stages in a feed-forward circuit topology to extend the possible multi-modulus control output values between the range of -1 to +1. A direct input receives an N-bit input control word which can be dithered, for example, by a sinewave in a two's complement format. The digital delta-sigma modulator can be of any type and includes cascaded accumulators and pipelined accumulator topologies.
|
