发明名称 Maintaining processor execution during frequency transitioning
摘要 An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.
申请公布号 US2003237012(A1) 申请公布日期 2003.12.25
申请号 US20020180836 申请日期 2002.06.25
申请人 JAHAGIRDAR SANJEEV;DERHALLI ISLAM;GEORGE VARGHESE;MANGRULKAR KEDAR;NAZARETH MATHEW 发明人 JAHAGIRDAR SANJEEV;DERHALLI ISLAM;GEORGE VARGHESE;MANGRULKAR KEDAR;NAZARETH MATHEW
分类号 G06F1/08;(IPC1-7):G06F1/04 主分类号 G06F1/08
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