发明名称 Semiconductor memory device with reduced package test time
摘要 The present invention relates to a semiconductor memory device and, more particularly, to package and test technique of a semiconductor memory device. An object of the present invention to provide a semiconductor memory device capable of performing a package test with bandwidth except for default bandwidth without any wiring modification with respect to package option pads. The present invention can implement the other package options except for the default package option determined by the wire bonding with internal option. When the package level test is to be performed using the other bandwidth except for the bandwidth corresponding to the default package option, it is unnecessary to modify the wiring. Since the test can be performed with the upper bandwidth than the bandwidth corresponding to the default package option, the package test time can be reduced. For this, the buffer control signals are used which control the VDD or VSS applied to the package option pads via the wire bonding according to the operation mode. The buffer control signal can be generated using the mode register reset. The buffer receiving the buffer control signal outputs the signal corresponding to the wiring state of the package option pad, blocks the signal path from the package option pads, and outputs the signal corresponding to the package option except for the default package option.
申请公布号 US2003235090(A1) 申请公布日期 2003.12.25
申请号 US20020331728 申请日期 2002.12.31
申请人 LEE JUN-KEUN;LEE BYUNG-JAE 发明人 LEE JUN-KEUN;LEE BYUNG-JAE
分类号 G01R31/28;G11C11/401;G11C29/34;G11C29/48;H01L21/822;H01L27/04;(IPC1-7):G11C7/00 主分类号 G01R31/28
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