| 摘要 |
A test assembly (2000) for testing product circuitry (202, 302, 304) of a product die (2011, 300). In one embodiment, the test assembly includes a test die (2010, 400) and an interconnection substrate (2008) for electrically coupling the test die to a host controller (2002) that communicates with the test die. The test die may be designed according to a design methodology (100) for a test die and a product die that includes the step of concurrently designing test circuitry (202A, 402, 404) and product circuitry in a unified design (102). The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions (104) the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product die may contain some test circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers. |
