| 摘要 |
<p>A row decoder circuit (14) for use in programming a memory device. The row decoder circuit includes a means (13) for selecting the wordline of a memory cell to be programmed and a wordline of a memory cell to be programmed and a wordline driver circuit (100) that switches (15, 19) between a first power supply line (18) that supplies a programming voltage (VPROGRAM) and a second power supply line (16) that supplies a read/verify voltage (VVERIFY) in order to provide either the programming voltage or the read/verify voltage to the gate of a selected memory cell on the wordline (17). This switching between programming and read/verify voltages results in the programming pulses used to program the selected memory cell. The present invention allows for shorter programming pulses to be used and provides faster speeed in the overall programming of the memory cell.</p> |
