Apparatus and method for a frequency divider with an asynchronous slip

摘要

A frequency divider circuit utilizes an asynchronous slip request signal to provide an output clock signal according to a programmable divide ratio "R". A high frequency input clock signal has a frequency divided by a first factor to produce a divided signal when a slip signal is inactive. The output clock signal is produced by functionally dividing the frequency of the divided signal by a second factor. The second factor is determined by the programmable divide ratio divided by the first factor such that the frequency of the output clock signal is related to the frequency of the input clock signal and the programmable divide ratio. An asynchronous slip request signal is generated when the programmable divide ratio is a non-multiple of the first factor. The asynchronous slip request signal activates the slip signal such that a transition of the divided signal is skipped.