发明名称 |
RAM data array configured to provide data-independent, write cycle coherent current drain |
摘要 |
An apparatus and method for forming a RAM data memory that generates predictable noise/interference components that are coherent with each write cycle and essentially independent of the data content of the RAM data memory. The RAM data memory is comprised of a plurality of cells, each representing a data bit, which are selectively addressable as memory bytes formed of multiple bits. Each cell is formed of two sets of cross-coupled transistors. By causing each set of cross-coupled transistors to be set to a common voltage level at the beginning of a write cycle before setting one set of transistors to a low level and the one set of transistors to be set to a high level (thus representing a desired data bit value), the associated noise/interference components of the power drain are data independent. Furthermore, the data-independent noise occurs at frequencies at or above the write cycle rate.
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申请公布号 |
US6667923(B1) |
申请公布日期 |
2003.12.23 |
申请号 |
US20020205862 |
申请日期 |
2002.07.26 |
申请人 |
ALFRED E. MANN FOUNDATION FOR SCIENTIFIC RESEARCH |
发明人 |
DELMAIN GREGORY JAY;GORD JOHN;KARR LAWRENCE J.;DE ROCCO PAUL;DEMICHELE GLENN A.;KERNS DOUGLAS;BARBER ANDREW |
分类号 |
G11C7/10;(IPC1-7):G11C7/02 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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