Integrated circuit having an EEPROM and flash EPROM using a memory cell with source-side programming

摘要

In accordance with one embodiment of the present invention, a non-volatile integrated circuit memory includes a flash EPROM array having a first plurality of memory cells, and an EEPROM array having a second plurality of memory cells arranged along rows and columns. Each of the first and second plurality of memory cells has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a floating gate and a select gate. The EEPROM array further includes a plurality of data lines each being coupled to the drain regions of a plurality of cells along at least a portion of a column of cells, and a plurality of source lines each being coupled to the source regions of a plurality of cells along at least a portion of a row of cells.