发明名称 SELF ALIGNED COMPACT BIPOLAR JUNCTION TRANSISTOR LAYOUT, AND METHOD OF MAKING SAME
摘要 The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate (112). Thereafter, a spacer (136) is formed at the topology. A base layer (140) is formed from epitaxial silicon above the spacer (136) and at the topology. A leakage block (158) is formed in the substrate by out-diffusion from the spacer (136). Thereafter a BJT is completed with the base layer (140) and the spacer (136).
申请公布号 WO03050876(A3) 申请公布日期 2003.12.18
申请号 WO2002US39405 申请日期 2002.12.10
申请人 INTEL CORPORATION 发明人 BOHR, MARK;AHMED, SHAHRIAR;CHAMBERS, STEPHEN;GREEN, RICHARD;MURTHY, ANAND
分类号 H01L21/331 主分类号 H01L21/331
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