| 摘要 |
A microprocessor includes a plurality of execution units (60A,60B,60C) each configured to execute instructions and an instruction dispatch circuit (52) configured to dispatch instructions for execution by the plurality of execution units. A power management control unit (50) includes a programmable unit (51) for storing information specifying one or more reduced power modes. In the implementation of a first performance throttling technique, the power management control unit may be configured to cause the instruction dispatcher to limit the dispatch of instructions to a limited number of execution units. In the implementation of a second performance throttling technique, the power management control unit may be configured to limit the dispatch of instructions from the instruction dispatcher on every cycle, upon every other cycle, upon every third cycle, upon every fourth cycle, and so on. In the implementation of a third performance throttling technique, the power management control unit may be configured to control the dispatch of instructions from a floating-point scheduler (56) to one or more floating-point execution pipelines (58A,58B,58C). |
