发明名称 SEMICONDUCTOR TEST APPARATUS
摘要 <p>An excellent failure/no-failure test of devices can be realized by measuring the cross point of a differential clock signal CLK outputted from DUT and the timings of two data signals DATA to obtain a relative phase difference between the two signals. There are provided differential signal timing measuring means that outputs cross point information Tcross obtained by measuring the timing of the cross point of one differential output signal outputted from a device to be tested; non-differential signal timing measuring means that outputs data change point information Tdata obtained by measuring a transition timing at which the logic of the other non-differential output signal outputted from DUT transitions; phase difference calculating means that outputs a phase difference ΔT obtained by calculating the relative phase difference between the cross point information Tcross obtained by measuring the two output signals at the same time and the data change point information Tdata; and failure/no-failure test means receptive of the phase difference ΔT for performing, based on a predetermined threshold value, a failure/no-failure test in the relative phase relationship of DUT.</p>
申请公布号 WO2003104826(P1) 申请公布日期 2003.12.18
申请号 JP2003007315 申请日期 2003.06.10
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