发明名称 HIGH PERFORMANCE IP PROCESSOR FOR TCP/IP, RDMA AND IP STORAGE APPLICATIONS
摘要 An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer (2) through full TCP/IP termination and deep packet inspection through Layer (7). A set of engines performs pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing, based at least in part on the classification. An internal memory or local session database cache stores a TCP/IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
申请公布号 WO03104943(A2) 申请公布日期 2003.12.18
申请号 WO2003US18386 申请日期 2003.06.10
申请人 PANDYA, ASHISH, A. 发明人 PANDYA, ASHISH, A.
分类号 G06F15/173;G06F15/177;H04L29/06;H04L29/08 主分类号 G06F15/173
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