| 摘要 |
PURPOSE: A device for saving a bus line of a processor is provided to cut a number of the bus lines by half by transmitting a signal transmitted from each data bus line of the processor after phase shift. CONSTITUTION: The processor(100) generates a phase difference by respectively shifting a phase of a processed information signal and an address signal of the processed information signal stored in peripheral devices(130), and outputs it through respective data bus lines. An address bus transmits the address signal as a bus line number corresponding to the half of the address signal bits. An information bus transmits the information signal as the bus line number corresponding to the half of the information signal bits. The peripheral devices receive the address signal from the processor through an address bus line(110) and an information bus line(120), and transmit/receive the information signal. A clock(140) generates and outputs a clock signal operating the processor and the peripheral device in a synchronous state.
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