发明名称 Multistage level discrimination circuit
摘要 A level discrimination circuit includes two offset compensation circuits. Each offset compensation circuit receives a differential pair of input signals, detects their peak values, and adds the peak value of each input signal to the other input signal, thereby generating an offset-compensated differential pair of output signals. The output signals of the first offset compensation circuit are used directly as the input signals of the second offset compensation circuit. The output signals of the second offset compensation circuit therefore have the correct duty cycle, and can be correctly discriminated by a comparator, even if the input signals to the first offset compensation circuit are burst signals in which each burst includes a large direct-current bias. This level discrimination circuit is suitable for receiving optical signals transmitted in bursts.
申请公布号 US2003231032(A1) 申请公布日期 2003.12.18
申请号 US20030448303 申请日期 2003.05.30
申请人 TANAKA TAKAYUKI 发明人 TANAKA TAKAYUKI
分类号 H03K5/08;H03K5/151;H04B10/04;H04B10/06;H04B10/14;H04B10/26;H04B10/28;(IPC1-7):H03K5/153 主分类号 H03K5/08
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