METHOD FOR GENERATING DESIGN CONSTRAINTS FOR MODULATES IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN SYSTEM

摘要

What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a timing budget by examining said estimated arrival times at said blocks pins.