发明名称 |
DRAM with total self refresh and control circuit |
摘要 |
Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.
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申请公布号 |
US2003231540(A1) |
申请公布日期 |
2003.12.18 |
申请号 |
US20020174867 |
申请日期 |
2002.06.18 |
申请人 |
NANOAMP SOLUTIONS, INC.;NANOAMP SOLUTIONS, INC. |
发明人 |
LAZAR PAUL S.;OH SEUNG CHEOL |
分类号 |
G11C11/406;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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