| 摘要 |
A function clock signal used to clock the execution of instructions in a serial peripheral interface based on a source clock signal is generated to have characteristics of one cycle per bit signal transmitted or received by the interface. The function clock signal is created by logically gating the source clock signal and a delayed copy of the source clock signal to create the function clock signal. The delayed copy of the source clock signal responds to edges of the function clock signal created by the logical gating, to create the function clock signal. In addition, the frequency of the function clock signal may be forced equal to the frequency of the source clock signal, which is useful to execute a single instruction for a repeated number of times. A rising edge of the function clock signal may also be made coincident to a rising edge of the source clock signal under such equal frequency circumstances.
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