发明名称 Synchronous mirror delay with reduced delay line taps
摘要 A synchronous mirror delay (SMD) clock recovery and skew adjustment circuit for an integrated circuit is described, having a reduced circuit implementation. The SMD clock recovery and skew adjustment circuit incorporates a delay segment into the forward delay line (FDL) and backward delay line (BDL) that accounts for all or some of the non-variable portion of the asserted clock signal time period. This delay segment allows reduction of the FDL and BDL lines to only those portions necessary to sense and adjust for the portion of the asserted clock signal time period that is variable and that must be adjusted for. The invention allows SMD clock recovery and skew adjustment circuits to be implemented in an optimized manner that exhibits a reduced overall circuit size.
申请公布号 US6665232(B2) 申请公布日期 2003.12.16
申请号 US20030369994 申请日期 2003.02.20
申请人 MICRON TECHNOLOGY, INC. 发明人 VAN DE GRAAFF SCOTT
分类号 G11C7/10;G11C7/22;(IPC1-7):G11C8/00 主分类号 G11C7/10
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