发明名称 |
Dynamic phase splitter circuit and method for low-noise and simultaneous production of true and complement dynamic logic signals |
摘要 |
A phase splitter circuit including a clock delay section, a signal converter section and a signal generator section. The clock delay section uses a clock signal to produce first and second delayed clock signals that are time delayed versions of the clock signal. The second delayed clock signal is delayed more than the first. The signal converter section converts a static logic signal to a dynamic logic signal dependent upon the clock signal and the first delayed clock signal. The signal generator section produces a pair of complementary dynamic logic output signals dependent upon the dynamic logic signal and the first and second delayed clock signals. One of the output signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal. A method for generating a pair of complementary dynamic logic signals from a static logic signal.
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申请公布号 |
US6664836(B1) |
申请公布日期 |
2003.12.16 |
申请号 |
US20020318517 |
申请日期 |
2002.12.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
WEN HUAJUN |
分类号 |
H03K5/151;(IPC1-7):H03K3/00 |
主分类号 |
H03K5/151 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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