| 摘要 |
An offset peak current mode control circuit is provided for use with a multiple-phase DC-to-DC voltage converter including a plurality of converter modules connected to a common load and having a common input voltage source, a current sensor coupled to a sensing resistor disposed in series between the common input voltage source and the load to derive a current sense signal corresponding to current passing through the sensing resistor, and a voltage error sensor coupled to the load to derive a voltage error signal corresponding to difference between an output voltage of the voltage converter and a reference voltage. When the DC-to-DC voltage converter is operated with a relatively low input voltage or a relatively high duty cycle resulting in an overlap of the current sense signal, the offset peak current mode control circuit utilizes information from the clean (i.e., non-overlapping) portion of the current sense signal, and then stretches the duty cycle applied to an associated voltage converter module so that it extends into the time of the overlapping portion of the current sense signal.
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