| 摘要 |
A high speed incrementer/decrementer design is presented that computes the propagate, generate, and kill signals which are used to compute carries and sums from the incrementer inputs. By setting one input to "0" and the carry-in to "1", the adder is used as an incrementer. In the design of the invention, a bit-wise decision is made whether to complement the input bit or not. The design also allows decrementing and supports both unsigned and 2's complement number representations.
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