发明名称
摘要 PROBLEM TO BE SOLVED: To execute efficient memory allocation by time-dividedly processing plural independent programs within one sampling time by a digital signal processor(DSP). SOLUTION: The memory address control device is constituted of selectors 1 to 3, 5, 8, 9, 11, a comparator 4, a difference unit 6, a complement converter 7, an adder 10, and latches 12, 13. Optional memory addresses to be accessed by respective programs can be set up by setting up offset addresses by the use of an offset register and a boundary of respective areas to be respectively accessed by these programs can be set up by an area register. Since memory access exceeding each area is not permitted, a memory area different in each job can be allocated. Even in programs have the same contents, access to the other memory can be inhibited in each job.
申请公布号 JP3479196(B2) 申请公布日期 2003.12.15
申请号 JP19970019661 申请日期 1997.01.20
申请人 发明人
分类号 G06F12/02;G06F9/46;G06F12/14;G10H1/02 主分类号 G06F12/02
代理机构 代理人
主权项
地址