| 摘要 |
<p>Conventionally, if a buffer is composed of a transistor having a large variation of element characteristics, the timing of an input clock pulse easily shifts from that of a reset pulse, failure may occur when the timing shift is large, and hence the operation margin with respect to the element characteristic variation becomes small. A timing generator circuit according to the invention is fabricated on an insulating substrate and has two TFFs (12, 13) for generating a dot clock DCK and a horizontal clock HCK having different frequencies in synchronism with a master clock MCK inputted from outside of the substrate. Separate reset pulses drst, hrst are generated by a pulse generator circuit (15) to reset the two TFFs (12, 13) at different timings. As a result, even if the variation of the element characteristics is large and even if the circuits are constituted of TFFs having rough process rules, the operation margin can be large.</p> |
