发明名称 |
Size-reduced majority circuit |
摘要 |
A majority circuit for reduce a size thereof is provided. The majority circuit is composed of a D/A converter converting a plurality of binary signals to an analogue signal, a majority determining circuit responsive to said analogue signal to achieve a majority operation on said plurality of binary signals to produce a result signal representative of a result of said majority operation.
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申请公布号 |
US2003227403(A1) |
申请公布日期 |
2003.12.11 |
申请号 |
US20030456355 |
申请日期 |
2003.06.05 |
申请人 |
NAKAGAWA HIROSHI;OISHI KANJI |
发明人 |
NAKAGAWA HIROSHI;OISHI KANJI |
分类号 |
H03M1/80;H03K19/23;(IPC1-7):H03M1/66 |
主分类号 |
H03M1/80 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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