Semiconductor integrated circuit, design support apparatus, and test method

摘要

There is disclosed a semiconductor integrated circuit comprising a logic BIST circuit which includes a test pattern generator and test result compressor and which performs a built-in self test (logic BIST) of a logic circuit, a pattern counter which counts test patterns during the logic BIST, an expected value comparison circuit which compares a compressed value output of the test result compressor with an expected value input from an external tester for each test pattern and which outputs a failure flag at a mismatch detection time, an external terminal which outputs the failure flag from the LSI, and an external terminal which outputs from the LSI a pattern count signal at a time when the pattern counter receives the failure flag.