A method and apparatus for reducing clock skew by isolating powe r distribution to a clock tree from chip logic is provided. Further, the present invention uses separate leads through a circuit board to distribute power from a power supply to a clock tree and a chip logic.
申请公布号
WO03017071(A3)
申请公布日期
2003.12.11
申请号
WO2002US25916
申请日期
2002.08.14
申请人
SUN MICROSYSTEMS, INC.
发明人
LIU, DEAN;THORP, TYLER, J.;TRIVEDI, PRADEEP, R.;YEE, GIN, S.