发明名称 Power limiting time delay circuit
摘要 A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.
申请公布号 US2003227729(A1) 申请公布日期 2003.12.11
申请号 US20020166876 申请日期 2002.06.11
申请人 STMICROELECTRONICS, INC. 发明人 WENZEL EDWARD P.
分类号 G05F1/569;(IPC1-7):H02H3/027 主分类号 G05F1/569
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