PARTIALLY DEPLETED SOI MOSFET WITH SELF-ALIGNED BODY TIE

摘要

A silicon-on-insulator (SOI) device structure 100 formed using a self-aligne d body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed a nd yield of the device may be increased. In addition, the process flow minimize s the sensitivity of critical device parameters due to misalignment and critic al dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.