发明名称 |
Method and apparatus for simulating conditional branch instructions in a simulator which implies binary translation |
摘要 |
In an embodiment, a binary translator translates instructions from a simulated instruction set into instructions from a host instruction set for execution on a host processor. The binary translator may translate a simulated conditional branch instruction into a set of host branch instructions. The binary translator may substitute a host target address for a simulated target address in a selected host branch instruction for an in-page conditional branch instruction.
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申请公布号 |
US2003229484(A1) |
申请公布日期 |
2003.12.11 |
申请号 |
US20020165853 |
申请日期 |
2002.06.07 |
申请人 |
LIOKUMOVICH IGOR;RAPPOPORT RINAT;LEVIT-GUREVICH KONSTANTIN;FISHTEIN ROMAN |
发明人 |
LIOKUMOVICH IGOR;RAPPOPORT RINAT;LEVIT-GUREVICH KONSTANTIN;FISHTEIN ROMAN |
分类号 |
G06F9/45;G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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