发明名称 PARTIALLY PATTERNED LEAD FRAMES AND METHODS OF MAKING AND USING THE SAME IN SEMICONDUCTOR PACKAGING
摘要 <p>A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal (100) formed into a web-like lead frame on one side. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts (113) only after the front side, including the chip (140) and wires (160), is hermetically sealed. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.</p>
申请公布号 WO2003103038(P1) 申请公布日期 2003.12.11
申请号 US2003013046 申请日期 2003.04.28
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