发明名称 |
Device for elaborating adresses for a digital signal processor |
摘要 |
<p>The processor program instructions include a code (CE) for elaboration of memory addresses. Each address register (ax,ay) is associated with an offset register (ox,oy), a modulo register (mx,my) and a configuration register (cx,cy). Each configuration register contains a set of predefined operating codes, each of which commands a predetermined computation in the computation circuit (28).</p> |
申请公布号 |
EP1369774(A1) |
申请公布日期 |
2003.12.10 |
申请号 |
EP20020291405 |
申请日期 |
2002.06.06 |
申请人 |
CSEMCENTRE SUISSE D'ELECTRONIQUE ET DEMICROTECHNIQUE SARECHERCHE ET DEVELOPPEMENT |
发明人 |
RAMPOGNA, FLAVIO;PFISTER, PIERRE-DAVID;MASGONTY, JEAN-MARC;PIGUET, CHRISTIAN |
分类号 |
G06F9/318;G06F9/355;(IPC1-7):G06F9/318 |
主分类号 |
G06F9/318 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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