Processor executing SIMD instructions

摘要

A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes an instruction "vxaddh Rc, Ra, Rb", an arithmetic and logic/comparison operation unit 41 and others ( i ) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, ( ii ) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc. <IMAGE>