发明名称 |
Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions |
摘要 |
An integrated circuit drain extension transistor. A transistor gate (72) is formed over a CMOS n-well region (10). A transistor source extension region (50), and drain extension region (52) are formed in the CMOS well region (10). A transistor region (90) is formed in the source extension region 50 and a transistor drain region 92 is formed between two drain alignment structures (74), (76) in the drain extension region (52).
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申请公布号 |
US6660603(B2) |
申请公布日期 |
2003.12.09 |
申请号 |
US20010952404 |
申请日期 |
2001.09.14 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MITROS JOZEF CZESLAW |
分类号 |
H01L21/28;H01L21/336;H01L21/8234;H01L21/8238;H01L27/088;H01L27/092;H01L29/06;H01L29/41;H01L29/423;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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