Phase-locked loop circuit

摘要

A phase error signal indicating a most recent phase difference between an input clock signal and a feed-back signal is produced in a phase comparing unit. Also, the phase difference of the phase error signal is monitored in an abnormal condition detecting unit. When the phase difference is higher than a threshold value, the abnormal condition detecting unit judges that the input clock signal is set in an abnormal condition, and a frequency-controlled clock signal is produced in the voltage controlled oscillator according to the phase error signal. Therefore, the oscillation clock signal can be output without changing a phase of the oscillation clock signal while suppressing wonders or jitters.