| 摘要 |
In a computer system with caching, memory transactions can retrieve and store groups of lines. Coherency states are maintained for groups of lines, and for individual lines. A single coherency transaction, and a single address transaction, can then result in the transfer of multiple lines of data, reducing overall latency. Even though lines may be transferred as a group, the lines can subsequently be treated separately. This avoids many of the problems caused by long lines, such as increased cache-to-cache copy activity. In one alternative, when a cache memory requests a group of lines, and when the group of lines is partially owned by another cache memory, then the requesting cache receives fewer than all the lines in the requested group.
|
