| 摘要 |
A system having several clock domains must have domain clocks properly aligned before powering up from a low-power or power-down mode. The domain clocks can be quickly aligned to enable fast system start-up if the clocks are forced into a rough alignment before a fine alignment process begins. Initially, a phase offset between the domain clocks is determined using a sync pulse, which indicates a location of one of the domain clocks relative to the other domain clock. Next, the domain clocks are forced into a minimum phase offset configuration by phase stalling one of the domain clocks. The phase stalling includes adjusting the pulse width of one of the domain clocks to force the clock into a rough alignment with the other domain clock. Finally, the domain clocks are fine aligned, and the system is placed into a normal power mode.
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