发明名称 |
Thread control system and method in a computer system |
摘要 |
The executing threads in CPU 100~103 are checked at random intervals in a specified range by interrupt execution modules 109~112, the results of the checks are stored in executing thread memory areas 113~116 and values of counters 117~120 that are corresponding to the executing threads are incremented. If the values of the counters 117~120 exceed specified values, applicable threads are judged to be operating abnormally and priorities of the applicable threads are lowered so as to prevent the abnormal operations of the threads. |
申请公布号 |
US6662204(B2) |
申请公布日期 |
2003.12.09 |
申请号 |
US20020173624 |
申请日期 |
2002.06.19 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
WATAKABE TAKESHI;HASEGAWA YOSHIAKI |
分类号 |
G06F9/46;G06F9/48;G06F11/34;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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