发明名称 Level converter circuit
摘要 In the level converter circuit, when input signal is L level, a first NMOS transistor and a first PMOS transistor P1 are turned on by a first power supply potential, a second power supply potential is output to a first output terminal, a second NMOS transistor is turned on, and thereby, a reference potential VSS is output to a second output terminal. On the other hand, when the input signal is H level, a third NMOS transistor is turned on, the reference potential is output to the first output terminal, a fourth NMOS transistor and a second PMOS transistor are turned on, and thereby, the first power supply potential VDH is output to the second output terminal.
申请公布号 US6661274(B1) 申请公布日期 2003.12.09
申请号 US20000698244 申请日期 2000.10.30
申请人 FUJITSU LIMITED 发明人 NAKA NAOAKI;NAKAMOTO JUNKO
分类号 H03K19/0185;H03K3/356;(IPC1-7):H03L5/00 主分类号 H03K19/0185
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