| 摘要 |
PURPOSE: A circuit for performing a special test mode and a semiconductor memory device using the same are provided to perform special tests of various modes at once by receiving control signals from an external pin. CONSTITUTION: An address buffer(207) is activated by a buffer enable signal(BUF_EN). The address buffer(207) receives an address(ADDN) from the outside according to a special test mode setting signal(SMT_SET) and transmits the address(ADDN) to a special test mode generator(205). The special test mode generator(205) is activated by the first external control signal(CS2HV). The special test mode generator(205) generates a special test mode setting signal(SMT_SET) according to the second external control signal(DNUI) and provides the special test mode setting signal(SMT_SET) to the address buffer(207). In addition, the special test mode generator(205) generates a special test mode specification signal by decoding the address(ADDN). A high voltage detector(201) receives a chip selection signal(CS2) from the outside and outputs the first external control signal(CS2HV). A control signal buffer portion(DNU) is activated by the first external control signal(CS2HV). The control signal buffer portion(DNU) receives a control signal(DNU) from an external pin and generates the second external control signal(DNUI).
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