| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress frequency variation before synchronization is established by shortening a PLL (phase-locked loop) drawing time when switching a reference clock. <P>SOLUTION: A selector 1 selects either one of a plurality of reference clocks REF1, REF2. The PLL is formed by an EX-OR type phase comparator 2, a low-pass filter 3, a voltage control oscillator (VCO) 4 and a 1/2 frequency divider 5. A flip-flop 6 receives output of the selector 1 and output P2 of the 1/2 frequency divider 5, respectively, on input terminals and outputs a 1/2 frequency divided pulse P1 with duty ratio of 50% to be changed according to the selected reference clock. The EX-OR type phase comparator 2 receives output P1 of the flip-flop 6 and the output P2 of the 1/2 frequency divider 5, respectively, and outputs an exclusive or (EX-OR). The voltage control oscillator (VCO) 4 generates an output clock CLK by controlling frequency according to output of the EX-OR type phase comparator 2. <P>COPYRIGHT: (C)2004,JPO |
