| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of performing a tRCD test adapted to the reduction in time between command inputs even when the test employs a memory testing apparatus inoperable for a high speed clock. SOLUTION: The semiconductor storage device is configured to include: a command decoder for respectively producing control signals corresponding to entered commands when receiving a plurality of kinds of the commands to set an ordinary operating mode; and a row address pre-latch circuit for storing a row address except a bank address received together with a precharge command when the semiconductor storage device is set to a test mode and outputting the row address to a row address latch circuit. The row address latch circuit holds a row address outputted from the row address prelatch circuit synchronously with a control signal generated by an input of an active command, and a column address latch circuit holds a column address having been already received at the input of the active command synchronously with a control signal produced by the input of either of a read command and a write command. COPYRIGHT: (C)2004,JPO
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