发明名称 DATA PROCESSING CIRCUIT FOR RECONFIGURABLE HARDWARE AND METHOD THEREFOR
摘要 <P>PROBLEM TO BE SOLVED: To provide a data processing circuit capable of reducing the capacity of input and output data, performing high speed input and output operations, freely realizing a compressor and an expander or the like at a required position and effectively utilizing hardware resources. <P>SOLUTION: The configuration information 1 of the data processing circuit is supplied to a compressor 2 along an arrow (data flow) shown in Figure. The capacity of data compressed via the compressor 2 is decreased. The compressed data whose capacity is made compact are stored as compressed data 3 according to a data flow indicated in the succeeding arrow. When the compressor 2 is replaced with an expander, the data flow follows the reversed arrows, and the expander restores the internal compressed data 3 into the configuration information 1 of the data processing circuit for further processes. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2003347927(A) 申请公布日期 2003.12.05
申请号 JP20020152847 申请日期 2002.05.27
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TSUBOI HIDEYUKI;SHIOZAWA TSUNEMICHI;INAMORI MINORU;NAKANE YOSHIKI
分类号 H03K19/173 主分类号 H03K19/173
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