| 摘要 |
The memory element comprises a set of n memory units (10-1,....,10-n), each with an address bus, a data bus, and a control bus connected respectively to the main address bus, the main data bus and the main control bus. The memory units comprise the elements of fuse/antifuse type allowing an irreversible registering of information. The control chain comprises the selection units (12-1,....,12-n) each generating a selection signal, that is a Chip-Select (CSi), where i is from 1 to n, for one of the memory units (10i) in a manner to allow an exclusive access to the selected memory unit. The selection units switch automatically the selection of memory units following the detection of a predetermined condition. The memory element allows to implement an equivalent of a programmable memory of the type few times programmable (FTP), and in particular of type FLASH. A memory circuit (claimed) comprises the memory units of programmable type. The memory element comprises the programmable memory units (10-1,...,10-n) each receiving a Status Bit (SBi) which allows to store an information on the end of selection, and the predetermined condition corresponds to writing the Status Bit in the respective memory unit. The selection units are connected in a chain which allows to compute the selection signal for the memory unit of rank i, and two selection signals, direct and inverse, S(i) and SN(i), are transmitted and received by the selection unit of rank i+1. The selection unit is in two embodiments. In the first embodiment, teh selection unit comprises a bistable of type D, an inverter, and three AND gates. In the second embodiment, the selection unit comprises an inverter and a NOR gate. Each memory unit is implemented by a technology of type CMOS, and the fusible elements are constituted by capacitors with thin oxide layers. |
