Memory device which is electrically programmable in an irreversible manner, comprises matrix of memory cells, each with a transistor and a capacitor with destructible dielectric

摘要

The memory device comprises a memory matrix (MM) of memory cells (CLij), each comprising an access transistor and a capacitor whose dielectric is compatible with a technology of type dynamic random-access memory (DRAM). Each row comprises a group of cells (CLi) whose gates of transistors are connected together by a first metallization (WLAi), and whose upper electrodes (ES) of capacitors are connected together by a second metallization (WLPi). Each column comprises a group of cells (CLj) whose sources of transistors are connected together by a third metallization (BLj). The memory control means (MCM) can apply the chosen voltages to the first, second and third metallizations in a manner to program selectively only one cell by breaking down its dielectric without programming other cells and without breaking down the transistors of all cells. A memory cell (CLij) is programmed by applying a gate voltage (Vg) to the first metallization (WLAi), and by applying a voltage difference sufficient to break down the dielectric of capacitor to the second (WLPi) and third (BLj) metallizations; the voltages applied to other metallizations are designed so to block the transistors of other cells of the memory matrix. The transistors of cells are of type n-MOS. The memory control means can apply the chosen voltages to the first, second and third metallizations in a manner to read selectively the logic contents of only one memory cell (CLij) without reading the contents of other memory cells. The memory device (claimed) is implemented in the form of an integrated circuit.