| 摘要 |
A bit synchronizing circuit that provides highly reliable data transmission at a high speed is provided. The circuit facilitates testing by using a plurality of clock signals that are generated based on a reference clock signal, each of the clock signals having unique phases. The circuit selects one of the clock signals as a writing clock signal that is suitable for a clock signal for synchronizing serial data, based on a synchronous timing signal. The synchronous timing signal is generated based on an edge signal that is generated based on an edge position of serial data. The edge position is determined for a plurality of groups of the clock signals, each group consisting of clock signals chosen every predetermined number of the clock signals.
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