发明名称 |
PC and ATE integrated chip test equipment |
摘要 |
The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.
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申请公布号 |
US2003226076(A1) |
申请公布日期 |
2003.12.04 |
申请号 |
US20020214846 |
申请日期 |
2002.08.08 |
申请人 |
KANG JONG-GU;KIM JONG-HYUN |
发明人 |
KANG JONG-GU;KIM JONG-HYUN |
分类号 |
G01R31/26;G11C29/56;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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