发明名称 INTEGRATED CIRCUIT DESIGN METHOD
摘要 A design method for designing an integrated circuit (IC) and a corresponding integrated circuit design tool are presented. An IC design having a plurality of building blocks (121-129) being interconnected by a plurality of interconnection wires (131-139) is represented by a two-dimensional representation (200) mimicking the positions of the building blocks (121-129) and interconnections (131-139) in the actual IC lay-out. The two-dimensional representation allows the IC designer to evaluate the lengths of the interconnection wires (131-139), which enablesthe IC designer to alter the IC design before the IC design back-end, e.g. the IC area optimization, is entered, thus leading to a more effective IC design method.
申请公布号 WO03100668(A2) 申请公布日期 2003.12.04
申请号 WO2003IB01839 申请日期 2003.04.25
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;DE OLIVEIRA KASTRUP PEREIRA, BERNARDO 发明人 DE OLIVEIRA KASTRUP PEREIRA, BERNARDO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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