发明名称 EFFICIENT READ, WRITE METHOD FOR PIPELINE MEMORY
摘要 <p>Methods and apparatus for efficiently writing data to and reading data from multi-state memory cells. According to one aspect of the present invention, a memory system includes a first storage element, a data source, a first element, a second element, and a ripple clock. The data source provides a plurality of bits to be stored in the first storage element, and the first element receives a first bit from the data source, and also clocks the first bit into the second element. The first element then receives a second bit of the plurality of bits from the data source substantially while the first bit is being stored into the first storage element. The ripple clock enables access to the first element and the second element such that the first bit and the second bit may be pipelined.</p>
申请公布号 WO2003100787(P1) 申请公布日期 2003.12.04
申请号 US2003005214 申请日期 2003.02.20
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