| 摘要 |
A digital frequency multiplier provides no-integer frequency multiplication of an input signal. A multiplier receives the input signal and an integer multiple of the input signal. A multiplier control signal selects/toggles which signal the multiplexer will output and how long. A counter, clocked by one of the signals, provides the multiplexer control signal. The multiplexer outputs a pre-determined number of clock cycles of each signal to produce the desired no-integer frequency multiplied input signal. The present invention generates frequency multiplication without a phase locked loop (PLL). |
