发明名称 |
Delay diagnosis method for semiconductor integrated circuit, computer program product for diagnosing delay of semiconductor integrated circuit and computer readable recording medium recording program thereon |
摘要 |
A delay diagnosis method is proposed that can avoid design steps from being retraced or repeated uselessly due to defective delay when we design a semiconductor integrated circuit including a plurality of blocks. This delay diagnosis method has the steps of inputting logic information and floor plan information, finding the number of start points connected to the end point of a path from the logic information, computing the logic stage number of the path from the number of start points, finding block-to-block distances from the floor plan information, computing intra-block delays from the logic stage number and gate unit-value delays, computing inter-block delays from the block-to-block distances and routing unit-value delays, and diagnosing if the delay of the path after logic synthesis can be converged within a target path delay from the relation among the computed intra-block delays and inter-block delays and the target path delay.
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申请公布号 |
US2003226126(A1) |
申请公布日期 |
2003.12.04 |
申请号 |
US20030393921 |
申请日期 |
2003.03.24 |
申请人 |
IWAI YOSHIHIRO;ISHII TATSUKI;SHIGEOKA KENJI;TOKUYAMA HIROTAKE |
发明人 |
IWAI YOSHIHIRO;ISHII TATSUKI;SHIGEOKA KENJI;TOKUYAMA HIROTAKE |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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